#ifndef _USTC_HIF_H_
#define _USTC_HIF_H_

#if (S3C44B0_TEST_PLATFORM>0)
#define HIF_BASE_ADDR		0x08000000	//S3C44B0
#define HIF_REG_DATA		(HIF_BASE_ADDR+0x00)
#define HIF_REG_ADDR		(HIF_BASE_ADDR+0x02)
#define HIF_IO_DATA			(HIF_BASE_ADDR+0x04)
#define HIF_TP_RW_CMD		(HIF_BASE_ADDR+0x06)
#else
#define HIF_BASE_ADDR		0x03000000
#define HIF_REG_DATA		(HIF_BASE_ADDR+0x00)
#define HIF_REG_ADDR		(HIF_BASE_ADDR+0x04)
#define HIF_IO_DATA			(HIF_BASE_ADDR+0x08)
#define HIF_TP_RW_CMD		(HIF_BASE_ADDR+0x0C)
#endif

#define HIF_USTC_IO_BASE_ADDR	0

//CMIF FIFO Entry of IO CTRL
#define HIF_CMIF_ENTRY		HIF_REG_ADDR

//Register of IO CTRL
#define HIF_AHB_ADDR		(HIF_USTC_IO_BASE_ADDR+0x04)
#define HIF_INT_STATUS		(HIF_USTC_IO_BASE_ADDR+0x08)
#define HIF_IO_BURST_LEN	(HIF_USTC_IO_BASE_ADDR+0x40)
#define HIF_SYS_CLK_EN		(HIF_USTC_IO_BASE_ADDR+0x48)
#define HIF_SYS_SW_RST		(HIF_USTC_IO_BASE_ADDR+0x4A)
#define HIF_CMIF_PCLK_SEL	(HIF_USTC_IO_BASE_ADDR+0x4C)
#define HIF_CMIF_MCLK_SEL	(HIF_USTC_IO_BASE_ADDR+0x4E)
#define HIF_CMIF_CLK_CTRL	(HIF_USTC_IO_BASE_ADDR+0x50)
#define HIF_GPIO_OUT		(HIF_USTC_IO_BASE_ADDR+0x54)
#define HIF_GPIO_DIR		(HIF_USTC_IO_BASE_ADDR+0x56)
#define HIF_PAD_CTRL		(HIF_USTC_IO_BASE_ADDR+0x58)
#define HIF_INT_CLEAR		(HIF_USTC_IO_BASE_ADDR+0x5C)
#define HIF_CMIF_FIFO_CTRL	(HIF_USTC_IO_BASE_ADDR+0x5C)
#define HIF_INT_MASK		(HIF_USTC_IO_BASE_ADDR+0x78)
#define HIF_PAD_STATUS		(HIF_USTC_IO_BASE_ADDR+0x7C)
#define HIF_PLL_CFG			(HIF_USTC_IO_BASE_ADDR+0x80)
#define HIF_TP_STATUS		(HIF_USTC_IO_BASE_ADDR+0x84)
#define HIF_CMIF_FIFO_R		(HIF_USTC_IO_BASE_ADDR+0x88)
#define HIF_CMIF_FIFO_W		(HIF_USTC_IO_BASE_ADDR+0x8C)
#define HIF_SYS_CTRL		(HIF_USTC_IO_BASE_ADDR+0x90)
#define HIF_YRC_PARA1		(HIF_USTC_IO_BASE_ADDR+0x94)
#define HIF_YRC_PARA2		(HIF_USTC_IO_BASE_ADDR+0x9C)


//HIF AHB Address control bits
#define HIF_IO_CMD_W		0x0000
#define HIF_IO_CMD_R		0x8000
#define HIF_IO_CMD_BURST	0x4000
#define HIF_IO_BYTE			0x2000

//HIF interrupt MASK bits
#define HIF_INT_MASK_ERR	0x0400
#define HIF_INT_MASK_CMIF_W	0x0800
#define HIF_INT_MASK_CMIF_R	0x1000
#define HIF_INT_MASK_SD		0x2000
#define HIF_INT_MASK_USB	0x4000
#define HIF_INT_MASK_CMIF	0x8000

//HIF interrupt statusbits
#define HIF_INT_STA_CMIF_W	0x0001
#define HIF_INT_STA_CMIF_R	0x0002
#define HIF_INT_STA_SD		0x0004
#define HIF_INT_STA_USB		0x0008
#define HIF_INT_STA_CMIF	0x0010
#define HIF_INT_STA_ERR		0x0020
#define HIF_INT_STA_TP		0x0040

//HIF CMIF FIFO Control bits
#define HIF_CFIFO_CTRL_SR	0x0010
#define HIF_CFIFO_CTRL_SW	0x0008

//HIF interrupt clear bits
#define HIF_INT_CLR_CMIF_W	0x0001
#define HIF_INT_CLR_CMIF_R	0x0002
#define HIF_INT_CLR_ERR		0x0004
#define HIF_INT_CLR_ALL		0x0007

//HIF system software reset bits
#define HIF_RST_SD			0x0001
#define HIF_RST_SD_REG		0x0002
#define HIF_RST_CMIF_LOGIC	0x0004
#define HIF_RST_CMIF_REG	0x0008
#define HIF_RST_USB			0x0010
#define HIF_RST_AHB			0x0020
#define HIF_RST_CFIFO		0x0300

//HIF system clock enable bits
#define HIF_CLK_EN_SD		0x0001
#define HIF_CLK_EN_CMIF		0x0002
#define HIF_CLK_EN_USB		0x0004
#define HIF_CLK_EN_USB_PHY	0x0008
#define HIF_CLK_EN_SD_RAM	0x0010
#define HIF_CLK_EN_CMIF_RAM	0x0060

//HIF CMR clk cfg
#define HIF_CMR_PCLK_EDGE	0x0001
#define HIF_CMR_MCLK_OUT	0x0002
#define HIF_CMR_PCLK_EXT	0x0004
#define HIF_CMR_EXT_PCLK_EDGE	0x0008
#define HIF_CMR_MCLK_EN		0x0010

#if (S3C44B0_TEST_PLATFORM==0)		//A7S
#define HIF_IO_DELAY()		__asm{nop}
#else
#define HIF_IO_DELAY()		ustc_delay(4)
#endif

extern void ustc_outh(USTC_U16 index, USTC_U16 data);
extern USTC_U16 ustc_inh(USTC_U16 index);
extern void ustc_reg_set(USTC_U16 index, USTC_U16 bits);
extern void ustc_reg_clr(USTC_U16 index, USTC_U16 bits);
extern void ustc_io_outw(USTC_U16 index, USTC_U32 data);//read IO without permiting USTC_IO_INT
extern void ustc_io_outw2(USTC_U16 index, USTC_U32 data);//read IO without protection, caller should avoid IO operation
extern void ustc_io_outb(USTC_U16 index, USTC_U8 data);	//read IO without permiting USTC_IO_INT
extern USTC_U32 ustc_io_inw(USTC_U16 index);			//read IO without permiting USTC_IO_INT
extern USTC_U32 ustc_io_inw2(USTC_U16 index);			//read IO without protection, caller should avoid IO operation
extern USTC_U8 ustc_io_inb(USTC_U16 index);				//read IO without permiting USTC_IO_INT
extern void ustc_io_burst_inw(USTC_U16 index, USTC_U32 * buf);
extern void ustc_io_burst_outw(USTC_U16 index, USTC_U32 * buf);
#endif
